1. Field of the Invention
Embodiments of the present invention relate generally to three-dimensional (3D) graphics processing and, more particularly, to tiled cache invalidation.
2. Description of the Related Art
Some graphics subsystems implement a tiling architecture in which a render target is divided into partitions referred to as tiles. Some tiling systems also store data in an on-chip cache memory during rendering, which increases performance and reduces memory bandwidth consumption. For improved performance, multiple processing entities may be provided to process the tiles in parallel.
One challenging aspect of processing data in this manner is managing data flow between the cache memory that stores the cache tiles and an external memory such as a frame buffer. Some intermediate data is only needed during a short processing interval and does not need to be written out from the cache memory to the frame buffer, which would unnecessarily consume memory bandwidth and power. In such situations, preventing cache entries from being written out to the frame buffer through the use of a cache invalidate command reduces the amount of memory bandwidth consumed.
In a graphics subsystem that implements a tiling architecture, cache invalidation is not straightforward. More specifically, when such an architecture reorders received primitives, the architecture must choose a time at which to execute a cache invalidate command that is received along with the primitives. However, if no mechanism exists to account for this discrepancy, or if the wrong time to execute the cache invalidate command is chosen, then there is a risk that the cache invalidate command is executed at a point in time that results in the wrong data being invalidated. Managing this risk is further complicated in a highly parallel tiling architecture that includes multiple processing entities.
As the foregoing illustrates, what is needed in the art is an effective way to invalidate data stored in an on-chip cache memory in a parallel tiled caching architecture.